`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Abu liu
// 
// Create Date: 2020/05/03 23:50:03
// Design Name: top
// Module Name: top
// Project Name: 
// Target Devices: xc7z020
// Target Board: zedboard
// Tool Versions: vivado 2019.1
// Description: Top entity of udp send module
// 
// Dependencies:
// 			
// 			
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

// Entire message:
//   MAC layer   |--MAC header--|-----------------------------------------|   
//   IP layer                   |--IP header--|---------------------------|
//   UDP layer                                |--UDP header--|------------|
//   user data                                               |----Data----|
//


module top (
    input xtalclk,
    input rstn,

    //GMII control signals
    output  wire    giganet_mdc,
    inout   wire    giganet_mdio,
    output  wire    giganet_rstn,
    output  wire    giganet_gtxclk,

    //GMII tx signals
    output  wire    [7:0]   giganet_tx,
    output  wire            giganet_tx_clk,
    output  wire            giganet_tx_er,
    output  wire            giganet_tx_en,

    //GMII rx signals
    input   wire    [7:0]   giganet_rx,
    input   wire            giganet_rx_clk,
    input   wire            giganet_rx_er,
    input   wire            giganet_rx_dv
);

wire    global_sync_rstn;
wire    pllclk_125mhz;
wire    pllclk_100mhz;
wire    pllclk_50mhz;

wire    [7:0]   data_to_send;


//global sync module, syncronize external reset and clock signals
global_sync global_sync_inst (
    .xtalclk(),         //external crystal clock signal, 100Mhz
    .ext_rstn(),        //external async reset signal

    .pllclk_125mhz(pllclk_125mhz),  //pll clock out, 125 Mhz
    .pllclk_50mhz(pllclk_50mhz),    //pll clock out, 50 Mhz
    .pllclk_100mhz(pllclk_100mhz),  //pll clock out, 100 Mhz
    .sync_rstn(global_sync_rstn)    //syncronized reset signal
);

//data generator
data_gen data_gen_inst (
    .sys_clk(pllclk_125mhz),
    .sys_rstn(global_sync_rstn),
    .data_out(data_to_send)
);

//udp sender
udp udp_inst (
    //interface to peripheral phy chip
    .mdc(giganet_mdc),
    .mdio(giganet_mdio),
    .rstn(giganet_rstn),
    .gtxclk(giganet_gtxclk),

    .tx_data(giganet_tx),
    .tx_clk(giganet_tx_clk),
    .tx_er(giganet_tx_er),
    .tx_en(giganet_tx_en),

    .rx_data(giganet_rx),
    .rx_clk(giganet_rx_clk),
    .rx_er(giganet_rx_er),
    .rx_dv(giganet_rx_dv),

    //system internal interface
    .sys_clk(pllclk_125mhz),
    .sys_rstn(global_sync_rstn),
    .fifo_send_data(data_to_send),
    .fifo_send_empty(),
    .fifo_recv_data(),
    .fifo_recv_full()
);


endmodule